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"Jongmin Jeong"

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"Jongmin Jeong"

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Material Removal Mechanism of CMP Pad by CVD Conditioner Cutting Edges
Jiho Shin, Jongmin Jeong, Yeongil Shin, Haedo Jeong
J. Korean Soc. Precis. Eng. 2026;43(7):671-677.
Published online July 1, 2026
DOI: https://doi.org/10.7736/JKSPE.026.00020
Pad conditioning restores degraded pad surfaces after wafer polishing in chemical mechanical planarization (CMP) using diamond-embedded conditioner discs. However, conditioning also causes pad cutting, thickness reduction, and profile deformation. While previous studies mainly focused on reducing pad cut rate (PCR) and improving profile uniformity, the fundamental cutting mechanism between conditioner cutting edges and the pad remains unclear. This study investigates the cutting mechanism using CVD conditioner discs with different cutting edge densities under varying conditioning loads to control contact area and load distribution. PCR and pad profile analyses revealed that cutting behavior is primarily governed by the load applied to individual cutting edges. Higher localized loads increased the contribution of cutting to overall material removal. In the pad edge region, where the conditioner partially overhangs the pad, altered contact geometry caused a transition in cutting mode. In this region, the number of active cutting edges had a greater influence than the load per edge. These findings clarify the cutting interactions between CVD conditioner edges and pad surfaces during conditioning and provide a physical foundation for optimizing conditioning parameters to improve pad management in CMP processes.
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Article
2-step CMP Strategy for Dishing Control of TGV Interposers
Seunghun Jeong, Yeongil Shin, Jongmin Jeong, Seonho Jeong, Haedo Jeong
J. Korean Soc. Precis. Eng. 2024;41(6):467-472.
Published online June 1, 2024
DOI: https://doi.org/10.7736/JKSPE.024.027
Chemical mechanical planarization (CMP) is an essential polishing process in semiconductor manufacturing. Advances in memory technology, including increased capacity and performance, have increased the importance of electronic packaging. In heterogeneous integration, the interposer acts as an important intermediary between the logic die and the substrate, solving numerous I/O bump problems in high-bandwidth memory (HBM) and logic chips. Traditionally, board-to-memory connections were made through wire bonding, which required additional space for wire connections and introduced latency due to extended signal transmission paths. A through-type approach has emerged as a solution that can significantly reduce waiting time and installation space by improving space efficiency and enabling vertical connections without extending wiring. Due to these new approaches, the importance of CMP is reemerging. Implementation of this important process requires precise control of the CMP dishing/protrusion of bonding surfaces. Improper selection of Cu pad dishing/protrusion can cause problems such as increased RC delay time and signal short circuit in the wiring. In this paper, we proposed a strategy to control dishing using CMP, especially for Through-glass-via (TGV).
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