Skip to main navigation Skip to main content
  • E-Submission

JKSPE : Journal of the Korean Society for Precision Engineering

OPEN ACCESS
ABOUT
BROWSE ARTICLES
EDITORIAL POLICIES
FOR CONTRIBUTORS
Article

TSV 기반 3차원 반도체 패키지 ISB 본딩기술

이재학, 송준엽, 이영강, 하태호, 이창우, 김승만

ISB Bonding Technology for TSV (Through-Silicon Via) 3D Package

Jae Hak Lee, Jun Yeob Song, Young Kang Lee, Tae Ho Ha, Chang-Woo Lee, Seung Man Kim
JKSPE 2014;31(10):857-863.
Published online: October 1, 2014
  • 7 Views
  • 0 Download
  • 0 Crossref
  • 0 Scopus
next

In this work, we introduce various bonding technologies for 3D package and suggest Insert-Bump bonding (ISB) process newly to stack multi-layer chips successively. Microstructure of Insert-Bump bonding (ISB) specimens is investigated with respect to bonding parameters. Through experiments, we study on find optimal bonding conditions such as bonding temperature and bonding pressure and also evaluate in the case of fluxing and no-fluxing condition. Although nofluxing bonding process is applied to ISB bonding process, good bonding interface at 270℃ is formed due to the effect of oxide layer breakage.

Download Citation

Download a citation file in RIS format that can be imported by all major citation management software, including EndNote, ProCite, RefWorks, and Reference Manager.

Format:

Include:

ISB Bonding Technology for TSV (Through-Silicon Via) 3D Package
J. Korean Soc. Precis. Eng.. 2014;31(10):857-863.   Published online October 1, 2014
Download Citation

Download a citation file in RIS format that can be imported by all major citation management software, including EndNote, ProCite, RefWorks, and Reference Manager.

Format:
Include:
ISB Bonding Technology for TSV (Through-Silicon Via) 3D Package
J. Korean Soc. Precis. Eng.. 2014;31(10):857-863.   Published online October 1, 2014
Close